Turning to FIG. 1, an example of a conventional system 100 can be seen. In this system 100, hosts 102-1 to 102-N (which can, for example, be a computer, router, or switch) are able to communicate with one another over communications medium 112 (which can, for example, be an optical fiber, backplane, or twisted pair) through network interfaces 104-1 to 104-N. In this example, the network interfaces 104-1 to 104-N employ Ethernet over Electrical Backplanes and, more specifically, 10 GBase-KR. A description of 10 GBase-KR can be found in the Institute of Electrical and Electronics Engineers (IEEE) standard 802.3-2008 (which is dated Dec. 26, 2008 and which is incorporated by reference herein for all purposes). These network interfaces 104-1 to 104-N employ media access control (MAC) circuits 106-1 to 106-N that communicate with physical transceivers (PHYs) 110-1 to 110-N via media independent interfaces (MIIs) 108-1 to 108-N (which can typically have half-duplex or full-duplex operation). Each of which is described in IEEE standard 802.3-2008.
Of interest here, however, are PHYs 110-1 to 110-N, and, as can be seen in greater detail in FIG. 2, PHYs 110-1 to 110-N (hereinafter PHY 110), PHY 110 employs several sublayers. This PHY 110 can be an independent integrated circuit (IC) or can be integrated with a MAC circuit (i.e., MAC circuit 106-1) and an MII 108. As shown, the PHY 110 is generally comprised of physical medium dependant (PMD) sublayer logic 212, physical medium attachment (PMA) sublayer logic 210, forward error correction (FEC) sublayer logic 204, and physical coding (PCS) sublayer logic 202. These sublayer logic circuits 202, 204, 210, and 212 interact with one another to provide communications between MII 108 and communications medium 112. For transmission, the FEC sublayer logic 204 employs an encoder 206 as described in IEEE standard 802.3-2008, clause 74, and, for reception, the FEC sublayer logic 204 employs a decoder 308 as described in IEEE standard 802.3-2008, clause 74.
Looking specifically to encoder 206 (which can be seen in greater detail in FIG. 3), it is able to encode multiple words from the PCS sublayer logic 202 into a frame. For example, the encoder 206 can encode 32 words, having 64 bits each (i.e., two header bits and 64 payload bits), into a frame having 2112 bits. As shown, the formatter 302 (which is generally comprised of input registers 312 and 314) receives the input data IN and aligns data format and transcode data. The converter 304 (which generally includes a transcoder and a 64b/66b converter) is able to generate a data word (i.e., 65-bit data word) from each input data word (i.e., 66 bits) by XORing one of the transcode bits with data bits (i.e., 8 data bits). These data words can then be provided to the reformatter 308 and the syndrome generator 306 and can have a polynomial representation m(x). The syndrome generator 306 (which generally includes 64-bit and 34-bit syndrome generators) can then generate parity bits (i.e., 32 parity bits) for each frame. Typically, the polynomial representation for these parity bits is:c(x)=p(x)+x32m(x)  (1)wherep(x)=x32m(x)mod g(x)  (2)andg(x)=x32+x23+x21+x11+x2+1  (3)The resulting frame would then include a payload having output data words followed by parity bits. For example, there can be 32 output data words (which each have one header bit and 64 data payload bits) concatenated with 32 parity bits, resulting in a frame size of about 2112 bits. The pseudorandom number generator 310 and combiner (which can generally function as a scrambler) can then scramble the frame using a (for example) 2112-bit pseudonoise sequence.
Some problems with this arrangement, however, are latency and bulkiness. Because formatter 302 employs input registers 312 and 314 there is a delay from the alignment, and, because conversion is split between the converter 304 and reformatter 308, a multi-cycle (typically two cycle) delay is introduced. Additionally, because of the bit lengths employed (i.e., 66 and 65 bits), 34-bit and 66-bit syndrome generators are employed. Therefore, there is a need for an improved encoder.
Some examples of conventional systems are: U.S. Pat. No. 7,499,500; U.S. Pat. No. 7,873,892; U.S. Pat. No. 8,108,756; U.S. Patent Pre-Grant Publ. No. 2009/0276681; U.S. Patent Pre-Grant Publ. No. 2010/0095185; U.S. Patent Pre-Grant Publ. No. 2010/0229067; and “IEEE Standard 802.3ap-2007: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Amendment 4: Ethernet Operation over Electrical Backplanes,” IEEE-SA Standards Board, Mar. 22, 2007; and IEEE Standard 802.3-2008 sections 1-5, Dec. 26, 2008 (which has been incorporated by reference above).